  nolist

* map331.hs .... 68331 Internal Register Map
* ===========================================

************************************************************************
*                                                                      *
*                  Copyright Hewlett-Packard Co. 1991                  *
*                                                                      *
************************************************************************


Y_331           equ             $F00000         ;Int'l stuff mapped low.

GPT             equ             $0FF900+Y_331   ;G.P. Timer Module
SIM             equ             $0FFA00+Y_331   ;System Integration Mod.
QSM             equ             $0FFC00+Y_331   ;Queued Serial Comm Mod.


* GPT Registers:
*---------------

TMCR            equ             $00+GPT         ;(W) Timer Config Reg
*               equ             $02+GPT         ;(W)
ICR             equ             $04+GPT         ;(W) Interrupt Config
PDDR            equ             $06+GPT         ;(B) Parallel Data Dir
PDR             equ             $07+GPT         ;(B) Parallel Data Reg
OC1M            equ             $08+GPT         ;(B) Out Compare 1 Mask
OC1D            equ             $09+GPT         ;(B) Out Compare 1 Data
TCNT            equ             $0A+GPT         ;(W) Timer Counter Reg
PACTL           equ             $0C+GPT         ;(B) Pulse Accum Control
PACNT           equ             $0D+GPT         ;(B) Pulse Accum Count
TIC1            equ             $0E+GPT         ;(W) Input Capture Reg 1
TIC2            equ             $10+GPT         ;(W) Input Capture Reg 2
TIC3            equ             $12+GPT         ;(W) Input Capture Reg 3
TOC1            equ             $14+GPT         ;(W) OutputCompare Reg 1
TOC2            equ             $16+GPT         ;(W) OutputCompare Reg 2
TOC3            equ             $18+GPT         ;(W) OutputCompare Reg 3
TOC4            equ             $1A+GPT         ;(W) OutputCompare Reg 4
TI4O5           equ             $1C+GPT         ;(W) In Capt 4/Out Cmp 5
TCTL1           equ             $1E+GPT         ;(B) Timer Control Reg 1
TCTL2           equ             $1F+GPT         ;(B) Timer Control Reg 2
TMSK1           equ             $20+GPT         ;(B) Timer I-Mask Reg 1
TMSK2           equ             $21+GPT         ;(B) Timer I-Mask Reg 2
TFLG1           equ             $22+GPT         ;(B) Timer I-Flag Reg 1
TFLG2           equ             $23+GPT         ;(B) Timer I-Flag Reg 2
CFORC_PWMC      equ             $24+GPT         ;(W) Cmp Force / PWM Ctl
CFORC           equ             $24+GPT         ;(B) Cmp Force - 1st half CFORC_PWMC
PWMC            equ             $25+GPT         ;(B) PWM CTL - 2nd half CFORC_PWMC
PWMA            equ             $26+GPT         ;(B) Pulse Wt Modulate A
PWMB            equ             $27+GPT         ;(B) Pulse Wt Modulate B
PWMCNT          equ             $28+GPT         ;(W) PWM Count Reg
PWMBUFA         equ             $2A+GPT         ;(B) PWM Buffer Reg A
PWMBUFB         equ             $2B+GPT         ;(B) PWM Buffer Reg B
PRESCL          equ             $2C+GPT         ;(W) GPT Prescaler
*               equ             $2E+GPT         ;(W)
*               equ             $3x+GPT         ;(16 bytes) GPT-Reserved


* map331.hs .... 68331 System Integration Module (SIM)
* =====================================================


* SIM Registers:
*---------------

SMCR            equ             $00+SIM         ;(W) SIM Config Reg
SIMTR           equ             $02+SIM         ;(W) SIM Test Register
SYNCR           equ             $04+SIM         ;(W) Clk Synthesizer Ctl
*               equ             $06+SIM         ;(B)
RSR             equ             $07+SIM         ;(B) Reset Status Reg
SIMTRE          equ             $08+SIM         ;(W) SIM Test Reg (E-Ck)
*               equ             $0A+SIM         ;(W)
*               equ             $0C+SIM         ;(W)
*               equ             $0E+SIM         ;(W)
*               equ             $10+SIM         ;(B)
PORTE           equ             $11+SIM         ;(B) Port E Data Reg
*               equ             $12+SIM         ;(B)
PORTE1          equ             $13+SIM         ;(B) Port E Data Reg (?)
*               equ             $14+SIM         ;(B)
DDRE            equ             $15+SIM         ;(B) Port E Data Dir.
*               equ             $16+SIM         ;(B)
PEPAR           equ             $17+SIM         ;(B) Port E Pin Assign
*               equ             $18+SIM         ;(B)
PORTF           equ             $19+SIM         ;(B) Port F Data Reg
*               equ             $1A+SIM         ;(B)
PORTF1          equ             $1B+SIM         ;(B) Port F Data Reg (?)
*               equ             $1C+SIM         ;(B)
DDRF            equ             $1D+SIM         ;(B) Port F Data Dir
*               equ             $1E+SIM         ;(B)
PFPAR           equ             $1F+SIM         ;(B) Port F Pin Assign
*               equ             $20+SIM         ;(B)
SYPCR           equ             $21+SIM         ;(B) Syst Protect Ctl
PICR            equ             $22+SIM         ;(W) Periodic Int Ctl
PITR            equ             $24+SIM         ;(W) Periodic Int Timing
*               equ             $26+SIM         ;(B)
SWSR            equ             $27+SIM         ;(B) SW Service Reg
*               equ             $28+SIM         ;(W)
*               equ             $2A+SIM         ;(W)
*               equ             $2C+SIM         ;(W)
*               equ             $2E+SIM         ;(W)
TSTMSRA         equ             $30+SIM         ;(W) Master Shift Reg A
TSTMSRB         equ             $32+SIM         ;(W) Master Shift Reg B
TSTSCA          equ             $34+SIM         ;(B) Shift Count Reg A
TSTSCB          equ             $35+SIM         ;(B) Shift Count Reg B
TSTRC           equ             $36+SIM         ;(W) Test Repetition Ctr
CREG            equ             $38+SIM         ;(W) Test Submodule Ctl
DREG            equ             $3A+SIM         ;(W) Test Distrib. Reg
*               equ             $3C+SIM         ;(W)
*               equ             $3E+SIM         ;(W)


* map331.hs .... 68331 System Integration Module (SIM)  (continued)
* =====================================================


* SIM Registers:  (continued)
* --------------

*               equ             $40+SIM         ;(B)
CSPDR           equ             $41+SIM         ;(B) Chip Sel Pin Data
*               equ             $42+SIM         ;(W)
CSPAR0          equ             $44+SIM         ;(W) C-Sel Pin Assign 0
CSPAR1          equ             $46+SIM         ;(W) C-Sel Pin Assign 1
CSBARBT         equ             $48+SIM         ;(W) C-Sel Base Add Boot
CSORBT          equ             $4A+SIM         ;(W) C-Sel Option Boot
CSBAR0          equ             $4C+SIM         ;(W) C-Sel Base Addr 0
CSOR0           equ             $4E+SIM         ;(W) C-Sel Option 0
CSBAR1          equ             $50+SIM         ;(W) C-Sel Base Addr 1
CSOR1           equ             $52+SIM         ;(W) C-Sel Option 1
CSBAR2          equ             $54+SIM         ;(W) C-Sel Base Addr 2
CSOR2           equ             $56+SIM         ;(W) C-Sel Option 2
CSBAR3          equ             $58+SIM         ;(W) C-Sel Base Addr 3
CSOR3           equ             $5A+SIM         ;(W) C-Sel Option 3
CSBAR4          equ             $5C+SIM         ;(W) C-Sel Base Addr 4
CSOR4           equ             $5E+SIM         ;(W) C-Sel Option 4
CSBAR5          equ             $60+SIM         ;(W) C-Sel Base Addr 5
CSOR5           equ             $62+SIM         ;(W) C-Sel Option 5
CSBAR6          equ             $64+SIM         ;(W) C-Sel Base Addr 6
CSOR6           equ             $66+SIM         ;(W) C-Sel Option 6
CSBAR7          equ             $68+SIM         ;(W) C-Sel Base Addr 7
CSOR7           equ             $6A+SIM         ;(W) C-Sel Option 7
CSBAR8          equ             $6C+SIM         ;(W) C-Sel Base Addr 8
CSOR8           equ             $6E+SIM         ;(W) C-Sel Option 8
CSBAR9          equ             $70+SIM         ;(W) C-Sel Base Addr 9
CSOR9           equ             $72+SIM         ;(W) C-Sel Option 9
CSBAR10         equ             $74+SIM         ;(W) C-Sel Base Addr 10
CSOR10          equ             $76+SIM         ;(W) C-Sel Option 10
*               equ             $78+SIM         ;(W)
*               equ             $7A+SIM         ;(W)
*               equ             $7C+SIM         ;(W)
*               equ             $7E+SIM         ;(W)


* map331.hs .... 68331 Queued Serial Communication Module (QSM)
* ==============================================================


* QSM Registers:
* --------------

QMCR            equ             $00+QSM         ;(W) QSM Config Reg
QTEST           equ             $02+QSM         ;(W) QSM Test Reg
QILR            equ             $04+QSM         ;(B) Interrupt Level Reg
QIVR            equ             $05+QSM         ;(B) Interrupt Vector
*               equ             $06+QSM         ;(W)
SCCR0           equ             $08+QSM         ;(W) SCI Control Reg 0
SCCR1           equ             $0A+QSM         ;(W) SCI Control Reg 1
SCSR            equ             $0C+QSM         ;(W) SCI Status Reg
SCDR            equ             $0E+QSM         ;(W) SCI Data Reg
*               equ             $10+QSM         ;(W)
*               equ             $12+QSM         ;(W)
*               equ             $14+QSM         ;(B)
QPDR            equ             $15+QSM         ;(B) QSM Port Data Reg
QPAR            equ             $16+QSM         ;(B) QSM Pin Assign Reg
QDDR            equ             $17+QSM         ;(B) QSM Data Dir Reg
SPCR0           equ             $18+QSM         ;(W) QSPI Control Reg 0
SPCR1           equ             $1A+QSM         ;(W) QSPI Control Reg 1
SPCR2           equ             $1C+QSM         ;(W) QSPI Control Reg 2
SPCR3           equ             $1E+QSM         ;(B) QSPI Control Reg 3
SPSR            equ             $1F+QSM         ;(B) QSPI Status Reg
*               equ             $20+QSM         ;(224 byte) QSM Reserved
REC_RAM         equ            $100+QSM         ;(32 byte) Receive RAM
TRAN_RAM        equ            $120+QSM         ;(32 byte) Transmit RAM
COMD_RAM        equ            $140+QSM         ;(16 byte) Command Ram
*
_REC_RAM        equ            $100+QSM         ;(32 byte) Receive RAM
_TRAN_RAM       equ            $120+QSM         ;(32 byte) Transmit RAM
_COMD_RAM       equ            $140+QSM         ;(16 byte) Command Ram


* Equates for setting register values:


* Chip Select Configuration

* Chip select size definitions: 8 bit or 16 bit port.
* Used only when the output is configured to be a chip select.
* Register: CSPAR0 (Chip Select Pin Assignment Register 0)
CSBT_16       equ  $0003       Boot chip select
CSBT_8        equ  $0002
CS0_16        equ  $000c       Bus Request pin
CS0_8         equ  $0008
CS1_16        equ  $0030       Bus Grant pin
CS1_8         equ  $0020
CS2_16        equ  $00c0       Bus Grant Acknowledge pin
CS2_8         equ  $0080
CS3_16        equ  $0300       FC0 pin
CS3_8         equ  $0200
CS4_16        equ  $0c00       FC1 pin
CS4_8         equ  $0800
CS5_16        equ  $3000       FC2 pin
CS5_8         equ  $2000
* Register: CSPAR1 (Chip Select Pin Assignment Register 1)
CS6_16        equ  $0003       A19 pin
CS6_8         equ  $0002
CS7_16        equ  $000c       A20 pin
CS7_8         equ  $0008
CS8_16        equ  $0030       A21 pin
CS8_8         equ  $0020
CS9_16        equ  $00c0       A22 pin
CS9_8         equ  $0080
CS10_16       equ  $0300       A23 pin
CS10_8        equ  $0200


* Sets pin to be either a discrete output or its default function.
* Register: CSPAR0 (Chip Select Pin Assignment Register 0)
BR_DO               equ  $0000      Bus Request
BR_DEFAULT          equ  $0004
BG_DO               equ  $0000      Bus Grant
BG_DEFAULT          equ  $0010
BGACK_DO            equ  $0000      Bus Grant Acknowledge
BGACK_DEFAULT       equ  $0040
FC0_DO              equ  $0000      FC0
FC0_DEFAULT         equ  $0100
FC1_DO              equ  $0000      FC1
FC1_DEFAULT         equ  $0400
FC2_DO              equ  $0000      FC2
FC2_DEFAULT         equ  $1000
* Register: CSPAR1 (Chip Select Pin Assignment Register 1)
A19_DO              equ  $0000      A19
A19_DEFAULT         equ  $0001
A20_DO              equ  $0000      A20
A20_DEFAULT         equ  $0004
A21_DO              equ  $0000      A21
A21_DEFAULT         equ  $0010
A22_DO              equ  $0000      A22
A22_DEFAULT         equ  $0040
A23_ECLK            equ  $0000      A23* discrete output is a 6809 E clock
A23_DEFAULT         equ  $0100

* Chip select block size in words NOT bytes.
* Registers: CSBARBT (Chip Select Base Address Register Boot)
*            CSBAR0 thru CSBAR10 (for selects 0 thru 10)
BLK_2K         equ  $0000
BLK_8K         equ  $0001
BLK_16K        equ  $0002
BLK_64K        equ  $0003
BLK_128K       equ  $0004
BLK_256K       equ  $0005
BLK_512K       equ  $0006
BLK_1M         equ  $0007

* Chip select options.
* Registers: CSORBT (Chip Select Option Register Boot)
*            CSOR0 thru CSOR10 (for selects 0 thru 10)
*
* Bus cycle qualification
AS_QUAL       equ  $0000         Address Strobe
DS_QUAL       equ  $0400         Data Strobe
* Byte option
BYTE_OFF      equ  $0000         Chip Select disabled
BYTE_LOWER    equ  $2000         Lower byte
BYTE_UPPER    equ  $4000         Upper byte
BYTE_BOTH     equ  $6000         Word access
* Bus mode
ASYNC         equ  $0000
SYNC          equ  $8000
* Active on R, W or Both
READ          equ  $0800
WRITE         equ  $1000
RD_WR         equ  $1800
* DSACK definition: define bus cycle termination used with this chip select
WAIT0         equ  $0000       Internally generated wait states
WAIT1         equ  $0040
WAIT2         equ  $0080
WAIT3         equ  $00c0
WAIT4         equ  $0100
WAIT5         equ  $0140
WAIT6         equ  $0180
WAIT7         equ  $01c0
WAIT8         equ  $0200
WAIT9         equ  $0240
WAIT10        equ  $0280
WAIT11        equ  $02c0
WAIT12        equ  $0300
WAIT13        equ  $0340
FAST          equ  $0380       Fast termination option
WAIT_EXT      equ  $03c0       External DSACK
* Space accessed by chip select
CPU_SP        equ  $0000       CPU space
USR_SP        equ  $0010       User space
SUP_SP        equ  $0020       Supervisor space
S_U_SP        equ  $0030       Supervisor & User space
* Interrupt priority level recognized by the chip select
IPL_ALL       equ  $0000       All levels
IPL1          equ  $0002
IPL2          equ  $0004
IPL3          equ  $0006
IPL4          equ  $0008
IPL5          equ  $000a
IPL6          equ  $000c
IPL7          equ  $000e
* Interrupt vector aquisition if chip select is configured to trigger on an IACK
AVEC          equ  $0001       Autovector enabled
NO_AVEC       equ  $0000       Disabled



* Register MCR (Module Configuration Register)
*
* Interrupt Arbitration bits
IARB0         equ  $0000       Reset value
IARB1         equ  $0001
IARB2         equ  $0002
IARB3         equ  $0003
IARB4         equ  $0004
IARB5         equ  $0005
IARB6         equ  $0006
IARB7         equ  $0007
IARB8         equ  $0008
IARB9         equ  $0009
IARB10        equ  $000a
IARB11        equ  $000b
IARB12        equ  $000c
IARB13        equ  $000d
IARB14        equ  $000e
IARB15        equ  $000f
* Show Cycle Enable bits
SHEN0         equ  $0000
SHEN1         equ  $0100
SHEN2         equ  $0200
SHEN3         equ  $0300
* Freeze the bus monitor enable (disable it)
FRZBM         equ  $2000
* Freeze the software enable (disable the watchdog and the periodic interrupt)
FRZSW         equ  $4000
* Module mapping: map internal registers to $FFF000 thru $FFFFFF
MM            equ  $0040
* Restrict the SIM registers to Supervisor mode access
SUPV          equ  $0080

MM_MSK        equ  $800000

* End of include file map331.hs
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